1. Technical Field
This disclosure relates to electronic circuits. Specifically, this disclosure relates to analog-to-digital conversion (ADC) and time-to-delay conversion (TDC).
2. Related Art
High-speed communication systems often have to combat inter-symbol-interference (ISI) that can severely impact a receiver's capability to recover the transmitted sequence. Usually an equalization technique is employed at the receiver to correct the channel induced interference. The ISI is generally data dependent and can include signal components with contributions based on prior (pre-cursor) and post (post-cursor) received signals. Various techniques exist, both in the literature and practice, to address pre-cursor and post-cursor ISI. Usually performed at the receiver, existing equalization techniques include attempts to undo the channel introduced interference as well as reconstruction of the ISI through detected signals. With the knowledge of the channel, pre-equalization can be applied at the transmitter to cancel the impact of channel at the receiver. Most of these techniques suffer from noise enhancement, error propagation or reduced dynamic range, and generally are not power and space efficient. Moreover, their performance also degrades considerably in high-speed channels, which can incur losses in excess of 25 dB.
While equalization techniques directly impact any receiver's performance in ISI-limited channels, their architecture, functionality and implementation are often dependent on other modules in the receiver. For example, if the equalizer is to be designed in the digital domain, the effective number of bits (ENOB) of the ADC is an important parameter for its performance. However, the ENOB or the signal to noise ratio of the ADC may degrade if the sampling clock has timing variations. In order to maintain timing accuracy, a clock-data recovery (CDR) circuit is imperative in the receiver as well.
Digital realization of the equalizer provides better performance compared to its analog counterpart mostly due to better tunability and implementation issues. However, the performance of digital equalizers directly depends on the number of bits coming out of the ADC. The power and size of an ADC increases exponentially with the number of bits, making the implementation of high-speed ADC with a higher number of bits prohibitive.
Usually flash or pipeline ADCs are used for high-speed applications. While the former uses a bank of comparators that grows exponentially with the desired number of bits, the latter requires complicated logics for time interleaving. Both of these options suffer from power/size inefficiency and may not be suitable for low-power, high-speed applications that require a higher number of bits. FIGS. 1A-1B relate to a conventional flash ADC. In FIG. 1A, input signal 104 is sampled based on clock signal 102. The sampled voltages (e.g., sampled voltage 106) are then provided as an input to a plurality of comparators. In order to achieve N-bit precision, conventional ADCs use O(2N) comparators whose reference voltages 108 are evenly spread across the dynamic range of input signal 104. FIG. 1B illustrates conventional ADC circuitry. Each comparator in fixed comparator bank 154 receives two inputs: the sampled analog input voltage and a fixed reference voltage. The outputs of the comparators are provided as inputs to thermometer-to-binary converter 152, which outputs an N-bit binary value that corresponds to the sampled analog input voltage. These ADCs consume a lot of power and use up a large amount of chip area because they require O(2N) comparators.
FIGS. 1C-1D relate to a conventional successive approximation register (SAR) ADC. The circuit shown in FIG. 1C uses only one comparator (as opposed to O(2N) comparators used in FIG. 1B), but requires multiple clock cycles to perform the conversion. Specifically, the output of the comparator is provided as an input to a successive approximation register (SAR), which converts the sampled analog input voltage (VIN) into a digital value by performing a binary search by using a digital to analog (DAC) converter. FIG. 1D illustrates how the reference voltage of the comparator (which is the output of the DAC) converges to the sampled analog input voltage over multiple clock cycles. Specifically, the input signal is first compared to the reference voltage that divides the entire dynamic range in two equal halves. This comparison generates the most significant bit (MSB) as well as selecting the next reference level. This process continues until N bits are generated in N cycles. Note that during these N cycles, the input to the comparator is held at the sampled value even though the input signal is changing. This makes SAR ADC unsuitable for high-speed applications where N additional clock cycles are needed for N bit resolution.
To summarize: in a flash ADC, the comparators are fixed with respect to the incoming signal and resolved N bits in one cycle, while in an SAR ADC the same comparator is updated in a decision-directed manner but requires N additional cycles to converge. There is a long felt need for an ADC that can operate at high speeds but which does not consume a large amount of power and which does not require a large area to implement.